Performance, thermal and power management system associated with an integrated circuit and related method

ABSTRACT

The performance, thermal and power management system is configured to perform DVFS calibration, temperature compensation adjustment, aging calibration, and DC offset calibration in an IC. The initial voltage supplied to the IC maybe set to an initial value which takes chip-to-chip process variations into account and then dynamically adjusted according to temperature variations, DC offset and/or aging effects. Therefore, the performance, thermal and power management system may achieve optimized thermal and power performance of the IC.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is a continuation application of U.S. application Ser. No. 13/719,193 filed on Dec. 18, 2012, which claims the benefit of U.S. provisional application No. 61/577,304 filed on Dec. 19, 2011.

BACKGROUND

Advances in semiconductor manufacturing technology have resulted in ever decreasing physical dimensions for the various circuit elements, such as, for example, field effect transistors, which are used in forming integrated circuits (ICs). Many ICs in a given electronic device have different functions and can operate at different frequencies. Typically, all ICs and/or all parts of a given IC may receive a voltage potential that is substantially uniform. However, as the market for consumer electronics is constantly improving, there is an increasing demand for smaller circuit packages that operate at increased speeds and consume less power for the purpose of conserving battery-life, such as in wireless communication applications. As such, one method of conserving power is to operate different ICs, or even different portions of a single IC, with a voltage that is optimized for an application use. Accordingly, power is conserved in the electronic device by not applying more than sufficient power for a given one or more of the ICs, according to the application use.

The voltage applied to a given IC for a given application use may be determined during production testing. However, environmental changes and process variations may change operating characteristics for the given IC, even subsequent to production testing of the given IC. For example, the frequency of the given IC for the given operation may vary with changes in temperature. Meanwhile, differences in transistor strength and performance variations may dictate different characteristic values that affect the operating frequency from one IC to another for the given application use.

In addition, through switching of semiconductor devices, the semiconductor material from which the semiconductor devices are made ages. As the semiconductor material of the IC ages, the transistors formed therein may be subject to deleterious effects. For example, PMOS transistors may be subject to negative biased temperature instability (NBTI), such that larger DC gate-to-source voltages are required for activation of the PMOS transistors. As another example, NMOS transistors maybe subject to channel hot carrier (CHC) effects, such that the NMOS transistors can be affected with higher slew, resulting in slower switching transitions at constant bias voltages. Due to the aging effect, higher voltage levels may be required for the transistors of the IC to operate with the same performance as during production testing.

Therefore, there is a need for providing a management system capable of optimizing performance, thermal characteristics and power consumption of ICs.

SUMMARY

The present invention provides a performance, thermal and power (PTP) management system associated with an integrated circuit. The PTP management system includes a performance circuit with adjustable configurations for simulating operations of the IC when receiving a supply voltage; a sensing module configured to measure a characteristic of the performance circuit; a memory for storing characterization data associated with the IC; and a PTP controller configured to set the performance circuit in a specific configuration according to the characterization data and adjust a level of the supply voltage according to the characteristic of the performance circuit.

The present invention also provides a method for managing performance, thermal and power of an integrated circuit. The method includes providing a performance circuit with adjustable configurations for simulating operations of the IC when receiving a supply voltage, providing characterization data associated with the IC, setting the performance circuit in a specific configuration according to the characterization data, and adjust a level of the supply voltage according to a characteristic of the performance circuit.

These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

Further details, aspects and embodiments of the invention will be described, by way of example only, with reference to the drawings. Elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. Like reference numerals have been included in the respective drawings to ease understanding.

FIG. 1 illustrates a functional diagram of a PTP management system in accordance with an aspect of the present invention.

FIG. 2 illustrates a diagram of a configurable PTP detector in the performance circuit in accordance with an aspect of the present invention.

FIG. 3 is a diagram illustrating the operation of the PTP management system when performing DVFS calibration in accordance with an aspect of the present invention.

FIG. 4 is a diagram illustrating the operation of the PTP management system when performing temperature compensation adjustment in accordance with an aspect of the present invention.

FIG. 5 is a diagram illustrating the operation of the PTP management system when performing DC offset calibration in accordance with an aspect of the present invention.

FIG. 6 illustrates a diagram of the performance circuit for performing aging calibration in accordance with an aspect of the present invention.

DETAILED DESCRIPTION

Certain terms are used throughout the following descriptions and claims to refer to particular system components. As one skilled in the art will appreciate, companies may refer to a component by different names. This document does not intend to distinguish between components that differ in name but not function. In the following discussion and in the claims, the terms “including” and “comprising” are used in an open-ended fashion, and thus should be interpreted to mean “including, but not limited to . . . . ” Also, the term “couple” or “couples” is intended to mean either an indirect or direct electrical connection. Thus, if a first device couples to a second device, that connection may be through a direct electrical connection, or through an indirect electrical connection via other devices and connections.

FIG. 1 illustrates a functional diagram of a performance, thermal and power (PTP) management system 100 in accordance with an aspect of the present invention. The PTP system 100 maybe implemented for a power management integrated circuit (PMIC), having one or more voltage potentials which may be adaptively scaled within the PMIC. Alternatively, the PTP system 100 may be implemented for one or more separate PMICs. In such implementations, the PTP system 100 may conserve power by providing an amount of voltage that is a minimum sufficient voltage for a given application use. As used herein, the term “application use” is used to describe a use of the PMIC for its intended function, such as in a consumer electronic device.

The PTP system 100 includes a PTP controller 12, a variable power supply 14, a memory 16, a sensing module 18 and a performance circuit 20. The PTP controller 12 is configured to control the operations of the variable power supply 14, the sensing module 16 and the performance circuit 20. The variable power supply 14 may be implemented to provide one or more voltage potentials (hereinafter referred to as V_(DD)) to one of more PMICs. In the embodiment depicted in FIG. 1, the variable power supply 14 is demonstrated as having a single output voltage V_(DD). However, it is to be understood that the variable power supply 14 may be configured to have multiple different outputs. In addition, the example of FIG. 1 is not limited to a single variable power supply 14, but may include a plurality of power supplies, each separately configurable by the PTP controller 12.

In the embodiments of the present invention, the memory 16 may be an eFuse, a flash memory, or any of a variety of memory types. The sensing module 18 may include one or multiple types of sensors, such as voltage sensor, temperature sensor, workload sensor or reliability sensor. The performance circuit 20 may include one or more PTP detector, each separately configurable by the PTP controller 12

FIG. 2 illustrates a diagram of a configurable PTP detector in the performance circuit 20 in accordance with an aspect of the present invention. Each PTP detector may include a plurality ring oscillators RO1-RO12 made of logic devices, such as NAND gates, NOR gates, inverters and any combination thereof. The number and configuration of the ring oscillators demonstrated in FIG. 2 are merely for illustrative purpose, and do not limit the scope of the present invention. Each ring oscillator may oscillate between states at a frequency that can be variable based on an applied voltage, which may be the voltage V_(DD) or another voltage supplied from the variable power supply 14 (not shown in FIG. 2) or another power supply. The PTP controller 12 may set the configuration of each PTP detector so as to vary its characteristics, such as NBTI or HCI sensibility. Each PTP detector may be implemented to set the voltage V_(DD) for a target performance, such as frequency, of an application use of the PMIC that may be specifically associated with the switching of NMOS devices, PMOS devices or any combination thereof.

Using a dynamic voltage and frequency scaling (DVFS) scheme, the PTP management system 100 of the present invention is configured to achieve optimized thermal and power performance of the PMIC by performing DVFS calibration, temperature compensation adjustment, aging calibration, and DC offset calibration. The purpose of DVFS calibration is to compensate chip-to-chip process variations of different PMICs and determine an optimized initial voltage V_(O) for operating a given PMIC at room temperature. The purpose of temperature compensation adjustment is to prevent the given PMIC from deviating from its target performance due to temperature variation and determine a corresponding compensation voltage ΔV_(TEMP). The purpose of DC offset calibration is to determine a compensation voltage ΔV_(DC) for compensating the voltage drop caused by inaccuracy or resistance of the given PMIC. The purpose of aging calibration is to determine a compensation voltage ΔV_(AGE) for compensating the performance degradation of the given PMIC due to aging effect. Thus, the voltage V_(DD) may be adaptively set to (V_(O)+ΔV_(TEMP)+ΔV_(DC)+ΔV_(AGE)) for optimizing thermal and power performance of the given PMIC. The operation of the PTP management system 100 will be explained in greater detail in the following paragraphs.

FIG. 3 is a diagram illustrating the operation of the PTP management system 100 when performing DVFS calibration in accordance with an aspect of the present invention. One or more characteristic numbers may be obtained for a given PMIC during production testing. For example, the relationship between the minimum voltage V_(MIN) (i.e. a minimum sufficient voltage for a given application use of the PMIC) and the operating frequency may be characterized by testing a plurality of substantially similar PMICs at room temperature. The characterization data (the voltage-frequency relationship of the PMIC) may then be stored in the memory 16.

In the embodiment depicted in FIG. 3, the horizontal axis represents the operating frequency, and the vertical axis represents the operating voltage. Curves SS, TT and FF represent the minimum voltage for operating devices made of slow silicon, typical silicon and fast silicon at a given frequency at room temperature, respectively. At a given voltage, the maximum operating frequency is limited by the device made of slow silicon with the lowest performance. At a given operating frequency, the maximum power is consumed by the device made of fast silicon. A characteristic number set may be obtained by performing linear approximation on the characterization data SS, TT and FF and stored in the memory 16. Therefore, the PTP controller 12 may retrieve a characteristic number corresponding to an operational frequency requested by the software of the given PMIC, thereby setting the initial voltage V_(O) with a minimum margin. In addition, different initial voltages for different application uses of the given PMIC may be set concurrently or at different times. As such, the PTP controller 12 can retrieve the necessary one or more characteristic numbers from characterization data stored in the memory 16 every time the PTP controller 12 sets the initial voltage V_(O), thereby minimizing the power consumption of the given PMIC for the given application use regardless of process variations.

FIG. 4 is a diagram illustrating the operation of the PTP management system 100 when performing temperature compensation adjustment in accordance with an aspect of the present invention. One or more characteristic numbers may be obtained for a given PMIC during production testing. For example, the relationship between the minimum voltage V_(MIN) (i.e. a minimum sufficient voltage for a given application use of the PMIC) and the operating frequency may be characterized by testing a plurality of substantially similar PMICs at a plurality of temperatures. The characterization data (the voltage-frequency-temperature relationship of the PMIC) may then be stored in the memory 16.

In the embodiment depicted in FIG. 4, the horizontal axis represents the temperature measured by the thermal sensor in the sensing module 18, and the vertical axis represents the amount of voltage adjustment ΔV_(TEMP). Curves T_(F1)˜T_(F4) represent the amount of voltage adjustment at a given temperature when operating at frequencies F1˜F4, respectively, wherein F1>F2>F3>F4. Therefore, the PTP controller 12 may retrieve a characteristic number ΔV_(TEMP) corresponding to the measured temperature and an operational frequency requested by the software of the given PMIC, thereby adjusting the voltage V_(DD) from V_(O) by an amount of ΔV_(TEMP) for compensating environmental variations.

FIG. 5 is a diagram illustrating the operation of the PTP management system 100 when performing DC offset calibration in accordance with an aspect of the present invention. One or more characteristic numbers may be obtained by measuring the crossover voltages of the performance circuit 20 set in various configurations. When a device operates at its crossover voltage, the operational frequency is least sensitive to the temperature. The characterization data (the crossover voltages of the performance circuit 20 in different configurations) may then be stored in the memory 16.

In the embodiment depicted in FIG. 5, the horizontal axis represents various configurations of the performance circuit 20 having different NBTI-sensitivity and HCI-sensitivity. The vertical axis represents the crossover voltage V_(CO) at which the operational frequency is least sensitive to the temperature. When detecting a DC offset in the given PMIC, the performance circuit 20 is set to a specific configuration whose crossover voltage V_(CO) best matches the PMIC voltage. The voltage supplied to the performance circuit 20 of the specific configuration is then adjusted for achieving the frequency target, thereby acquiring the DC offset voltage ΔV_(DC). Therefore, the PTP controller 12 may adjust the voltage V_(DD) from V_(O) by an amount of ΔV_(DC) which is least relevant to temperate, thereby accurately compensating the voltage drop caused by inaccuracy or resistance of the given PMIC.

FIG. 6 illustrates a diagram of the performance circuit 20 for performing aging calibration in accordance with an aspect of the present invention. In this embodiment, the performance circuit 20 includes two PTP detectors D1 and D2 may be made up of NBTI-sensitive and/or HCI-sensitive devices. Though identical in circuit structure, the PTP detectors D1 and D2 are powered by power supplies PS1 and PS2, respectively. In an operating life test (OLT) which simulates a long-period of work environment with accelerated temperature and voltage alterations in a short period of time, the non-aged PTP detector D1 is powered on by the power supply PS1 during the booting period and then powered off after the initialization is completed, while the aged PTP detector D2 is powered on by the power supply PS2 according to a system clock based on which the PMIC operates. In the embodiment depicted in FIG. 6, the PTP detectors D1 and D2 are demonstrated to have respective power supplies PS1 and PS2. However, it is to be understood that the PTP detectors D1 and D2 may also be supplied by the variable power supply 14 which is controlled by the PTP controller 12 according to different timing signals for providing respective power-on periods.

In the embodiment depicted in FIG. 6, the sensing module may measure the non-aged performance of the PTP detectors D1 and the aged performance of the PTP detectors D2. The aging compensation voltage V_(AGE) may be calculated based on the difference between the non-aged performance and the aged performance. Therefore, the PTP controller 12 may adjust the voltage V_(DD) from V_(O) by an amount of ΔV_(AGE), thereby compensating for the aging effects of the semiconductor material of the PMIC.

The PTP management system 100 of the present invention is configured to perform DVFS calibration, temperature compensation adjustment, aging calibration, and DC offset calibration. The voltage V_(DD) supplied to a PMIC may be set to an initial voltage which takes chip-to-chip process variations into account and then dynamically adjusted according to temperature variations, DC offset and/or aging effects. Therefore, the present invention may achieve optimized thermal and power performance of the PMIC.

Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims. 

What is claimed is:
 1. A performance, thermal and power (PTP) management system associated with an integrated circuit (IC), comprising: a performance circuit with adjustable configurations for simulating operations of the IC when receiving a supply voltage having a level set to a predetermined value for a given application use; a sensing module configured to measure a characteristic of the performance circuit; a memory for storing characterization data associated with the IC and the performance circuit, wherein the characterization data includes crossover voltages of the performance circuit in a plurality of configurations; and a PTP controller configured to: set the performance circuit in a specific configuration according to the characterization data; and adjust the level of the supply voltage according to the characteristic of the performance circuit.
 2. The PTP management system of claim 1, wherein: the performance circuit includes a first PTP detector and a second PTP detector having an identical circuitry; the PTP controller is further configured to: power on the first PTP detector during a booting sequence of the IC and power off the first PTP detector after the booting sequence of the IC ends; and power on the second PTP detector according to a system clock based on which the IC operates; and the sensing module is further configured to measure a non-aged performance based on the first PTP detector and measure an aged performance based on the second PTP detector.
 3. The PTP management system of claim 1, wherein: the sensing module is further configured to measure an IC voltage; and the PTP controller is further configured to set the performance circuit in a configuration corresponding to a crossover voltage commensurate with the IC voltage.
 4. The PTP management system of claim 3, wherein: the performance circuit includes a first PTP detector and a second PTP detector having an identical circuitry; the PTP controller is further configured to: power on the first PTP detector during a booting sequence of the IC and power off the first PTP detector after the booting sequence of the IC ends; and power on the second PTP detector according to a system clock based on which the IC operates; and the sensing module is further configured to measure a non-aged performance based on the first PTP detector and measure an aged performance based on the second PTP detector.
 5. The PTP management system of claim 3, wherein: the characterization data further includes a non-aged performance and an aged performance of the performance circuit; the sensing module is further configured to measure the non-aged performance and the aged performance of the performance circuit; and the PTP controller is further configured to set the performance circuit in a configuration commensurate with a voltage difference which is calculated based on a difference between the non-aged performance and the aged performance.
 6. The PTP management system of claim 5, wherein: the performance circuit includes a first PTP detector and a second PTP detector having an identical circuitry; the PTP controller is further configured to: power on the first PTP detector during a booting sequence of the IC and power off the first PTP detector after the booting sequence of the IC ends; and power on the second PTP detector according to a system clock based on which the IC operates; and the sensing module is further configured to measure the non-aged performance based on the first PTP detector and measure the aged performance based on the second PTP detector.
 7. The PTP management system of claim 1, wherein: the characterization data further includes a non-aged performance and an aged performance of the performance circuit; the sensing module is further configured to measure the non-aged performance and the aged performance of the performance circuit; and the PTP controller is further configured to set the performance circuit in a configuration commensurate with a voltage difference which is calculated based on a difference between the non-aged performance and the aged performance.
 8. The PTP management system of claim 7, wherein: the performance circuit includes a first PTP detector and a second PTP detector having an identical circuitry; the PTP controller is further configured to: power on the first PTP detector during a booting sequence of the IC and power off the first PTP detector after the booting sequence of the IC ends; and power on the second PTP detector according to a system clock based on which the IC operates; and the sensing module is further configured to measure the non-aged performance based on the first PTP detector and measure the aged performance based on the second PTP detector.
 9. A method for performance, thermal and power (PTP) management system associated with an integrated circuit (IC), comprising: providing a performance circuit with adjustable configurations for simulating operations of the IC when receiving a supply voltage; setting the level of the supply voltage to a predetermined value for a given application use; measuring crossover voltages of the performance circuit in a plurality of configurations and an IC voltage; setting the performance circuit in a configuration corresponding to a crossover voltage commensurate with the IC voltage; and adjust the level of the supply voltage according to a characteristic of the performance circuit.
 10. The method of claim 9, further comprising: powering on a first PTP detector of the performance circuit during a booting sequence of the IC and powering off the first PTP detector after the booting sequence of the IC ends; powering on a second PTP detector of the performance circuit according to a system clock based on which the IC operates; measuring a non-aged performance of the first PTP detector and an aged performance of the second PTP detector; calculating a voltage difference based on a difference between the non-aged performance and the aged performance; and setting the performance circuit in a configuration commensurate with the voltage difference. 